Workshop on Architectures and Languages for Throughput Applications(ALTA 2008 )Held in
conjunction with the 2008 International Symposium on Computer
Architecture (ISCA-35)
|
Person |
From |
Session |
Invited Talk Session |
||
Chuck Moore |
AMD |
Accelerated Computing in the Multi-core Era |
Havard Bjerke |
CERN |
High Throughput Computing for CERN's Large Hadron Collider |
Michael Shebanow |
NVIDIA |
GPU Computing: Pervasive Massively Multithreaded Processors
|
Douglas Carmean |
Intel |
TBD |
Weiwu Hu |
Chinese Academy of Sciences |
A Brief Introduction to Loongson Processors (Abstract) |
Sun Chan |
Simplight Electronics |
Towards a sequential programming model for a multi-threaded architecture |
Paper session |
||
Gabriel Loh |
Georiga Tech |
The Cost of Uncore in Throughput-Oriented Many-Core Processors |
Paul Peng |
Intel |
SEE: A Scalable Execution Environment for Heterogeneous Processing Architectures |
Wing-Yee Lo, Jiqiang Song, Daniel Pak-Kong Lun, Wan-Chi Siu |
Simplight Electronics |
SIMD Throughput Bottleneck Improvement Using Vector Load/Store and Configurable SIMD Support |
Changhai Zhao, Xiaohua Shi, Haihua Yan, and Lei Wang |
Beihang University |
Exploiting Coarse-Grained Data Parallelism in Seismic Processing |
Oscar Hernandez, Lei Huang, Barbara Chapman |
University of Houston |
Experiences Tuning an OpenMP Application |
Throughput-oriented applications are attracting broader interest because of the proliferation of multi- and many-core CPUs and GPUs. The reasons are many-fold. Increasing software-exposed parallelism is necessitated by power-constrained design. Moreover, the emphasis on visual quality in entertainment-oriented applications is driving demand on client platforms. Finally, the pre-existing demands for compute cycles in high-performance computing is challenged by the changing programming and optimization landscape found in highly integrated multi-core devices.
This workshop seeks an interdisciplinary set of commercial and academic researchers and practitioners working at the frontiers of throughput oriented programming models, applications, and architectures. These include, but are not limited to:
l Multi-core and many-core CPU and GPU architecture
l Proposed architectural enhancements for throughput computing
l Power considerations for throughput-oriented designs
l Data-parallel or collection-oriented programming models
l GPU programming models
l Domain specific languages
l Algorithmic techniques for implementing key building blocks for throughput computing algorithms
l Selected application case studies on throughput computing architectures, including (but not limited to)
n Gaming/Graphics
n Computational finance
n Seismic processing
n Image/Video/Signal processing
n Machine learning
n Web search and services
The workshop will combine a set of peer-reviewed submissions and invited talks.
Anwar Ghuloum (anwar.ghuloum@intel.com) Intel Corporation
Douglas Carmean Intel Corporation
Tom Conte North Carolina State University
Mike Houston AMD
Michael McCool RapidMind Inc.
Michael Garland Nvidia
Sun Chan Simplight Nanoelectronics
Xiaohua Shi Beihang University
Anwar Ghuloum (anwar.ghuloum@intel.com) Intel Corporation
Gansha Wu (gansha.wu@intel.com) Intel Corporation
Michael Liao (michael.liao@intel.com) Intel Corporation
Josh Fryman (joshua.b.fryman@intel.com) Intel Corporation